IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS { II : ANALOG AND DIGITAL SIGNAL PROCESSING 1 A Four - Quadrant Floating - Gate

| Four-quadrant synapse stuu In our rst treatments of single-transistor synapses ((1], 2]; elaborated in 3]), we presented the electron-tunneling, hot-electron{injection, and multiplicative behavior of these devices. We used a feedback connguration to characterize the tunneling and hot-electron injection phenomena in these synapses 3]. We also derived an eeective learning rule, but we did not consider any speciic ways that these synapses could be used in a network. Our presentation of the autozeroing oating-gate ampliier (AFGA) 5], 6] showed the rst circuit applications of a single-transistor synapse with continuous oxide currents. In another paper , we generalized the AFGA synapse connguration to consider the behaviors that emerge when single-transistor synapses are coupled together to form various continuous-time learning networks 7]. This paper began to consider these oating-gate devices as continuous-time circuit elements. This paper presents the next fundament a oating-gate synapse that computes four-quadrant products of its input and weight value, and computes a four-quadrant correlation of the input and output or error function variables. *** need to say something of why four-qudrant computations are important, why they are diicult, etc. *** Four quadrant operation is essential in most adaptive lter and neural network applications. Biological synapses have only seem to have two-quadrant behavior, but ..... ** make this paragraph smaller ** Our oating-gate synapses possess ve important necessary to build adap-tive analog VLSI systems 1], 4]. First, in the absence of learning, the weight is stored permanently; because the oating gate is surrounded by SiO 2 , charge leakage is negligible. Second, when operated with subthreshold currents, the synapse's output current is the product of the input signal with the synaptic weight. Third, the synapse requires minimal area, because it comprises only one or two transistors. Fourth, the synapse dissipates a minimal amount of power, because it operates at subthreshold current levels. Fifth, the synapse implements a learning rule for modifying the weight on the oating gate; the form of this rule depends on how various error signals are fed back to the oating gate. In Section I, we review the source-degenerated pFET synapse, and present the operating conditions that we will (a) (b) Fig. 1. The source-degenerated (s-d) pFET synapse. (a) Circuit diagram of the s-d pFET synapse. The s-d pFET synapse is comprised of a pFET single-transistor synapse and the x diode element, which provides feedback to the source terminal. This feedback results in a weaker exponential …